Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor.

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• Microprocessor And Interfacing

Interfacing IO devices with 8085. Memory interfacing with 8085 microprocessor. Interfacing with 8085 Microprocessor Part-24 for gate isro.

• The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM. • Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are connected to 13 address pins of all the memory. • The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chip select signals.

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Microprocessor And Interfacing

• These four chip select signals can be used to select one of the four memory IC at any one time. • The address line A15 is used as enable for decoder. • The simplified schematic memory organization is shown.